The fabrication of integrated circuits (“IC”) devices involves the performance of a range of processing steps. In particular, patterned layers of various materials are applied to a substrate to create the desired device. The patterns of the layers must be accurately aligned to ensure proper operation of the resultant circuit. Misalignment of the layers will at best degrade the performance of the IC and at worst render it completely inoperative. As IC designs have become increasingly complex the critical dimensions (“CDs”) thereof have been correspondingly reduced, resulting in a reduction in acceptable relative displacement of the various IC device layers.
Currently, most semiconductor devices are manufactured using photolithographic techniques, which involve exposure of a photoresist layer of a substrate to a pattern and the subsequent development of the pattern into permanent form. Semiconductor pattern overlay is the measure of vector displacement from one layer of the IC to another layer. The overlay requirements for a particular IC design are typically determined through a combination of CDs and overlay excursion. When an immersion scanner is used during the exposure process, overlay performance is impacted by internal stresses caused by any change in the pressure of the lens cooling water (“LCW”) disposed within a cooling water channel of the wafer table for stabilizing the temperature of the wafer.